[SEU News Network, August 2nd] (Correspondent: Zhang Jingwei) Recently, the 60th Design Automation Conference (DAC) and System Design Contest (SDC) hosted by Electrical and Electronics Engineers (IEEE) and the Association for Computing Machinery (ACM) were convened in San Francisco, USA. In the SDC, the SEUer team successfully defended their championship in the FPGA track, securing the first place in the 60th DAC-SDC contest and becoming the only team to achieve a “two-peat” victory in the event, setting a new record beyond technical prowess. In addition, the SEU AI2023 team won the second place in the GPU track.
The DAC is a top conference of its
kind in the field of Electronic Design Automation (EDA) and chip (architecture)
planning, hosted by IEEE and ACM alternatively on the annual basis. The SDC
organized by the DAC is the highest-level contest in both the academia and the
industry for accelerating AI in microsystem design. The results of each contest
are announced at the DAC held in the same year. This year, in addition to the
FPGA track initiated since last year, the GPU track has also been renewed.
This year’s competition in the FPGA track was more
intense than that in previous years. On the basis of maintaining the
requirements of edge computing and high-speed low-power consumption, there was
a change from single-object detection tasks to multi-object detection tasks,
imposing stricter algorithm requirements on participating teams. Faced with
these new challenges, the SEUer team embarked on the competition once again,
competing fiercely with the top teams from over 40 organizations worldwide.
After three cycle tests in March, May, and June, as well as the final
submission of their solution, the SEUer team gained the champion once againwith a total score of 122.1 points by virtue of their F1 recognition
accuracy of 0.504 and excellent performance of 480fps, securing the first
place in the FPGA track of SDC. The AI2023 team, led by SEU and
involving collaboration among the industrial, academic, and research
institutes, continuously refined their design over a period of three months.
They finally achieved the second place globally in the GPU track in the
SDC, with a high-performance F1 accuracy of 0.585 and a speed of 59 FPS.
The FPGA team was jointly guided by Prof. Yang Jun
and Researcher Zhang Meng from the School of Integrated Circuits and the School
of Electronic Science and Engineering, SEU. The team members included Ph.D.
students Zhang Jingwei and Shen Chaoyao, and master students Cui Zenan and Cao
Xinye. The GPU team was guided by Researcher Zhang Meng from the School of
Integrated Circuits and the School of Electronic Science and Engineering, and
technically supported by Ph.D. student Shen Chaoyao. The team members included SEU
Ph.D. students Ji Yuning, Chen Ziyang, Chen Guangyuan, and the master student Ma
Yiming, as well as engineers Li Guoqing, Jing Wenlin, and Li Tuo from the industrial,
academic, and research collaboration institutes.
It is reported that the DAC is a Class-A conference
recommended by China Computer Federation (CCF). The SDC was co-founded by the DAC and world’s top
technology companies several years ago, which aims to encourage participating
teams to achieve algorithmic innovation and utilize hardware-software
co-optimization methods to improve the hardware of computer vision
microsystems, enabling efficient operation of artificial neural networks and
other sophisticated microsystems. The competition is highly competitive with
a large number of participating teams and has a considerable influence on both
academia and industry.
Submitted by: School of Integrated Circuits and School of Electronic Science and Engineering, SEU
Translated by: Melody Zhang
Reviewed by: Ma Xingcheng
Edited by: Kong Haoxuan
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